1. Field of the Invention
The present invention relates to a MOS semiconductor device and, more particularly, to a MOS semiconductor device of the type including a gate electrode which has a double-layer structure and a method of fabricating such a MOS semiconductor device.
2. Description of the Prior Art
There has been introduced in the semiconductor devices art a MOS semiconductor device having a gate electrode layer which is produced by laminating two sublayers on a gate oxide layer of a MOS transistor. Such a double-layer gate electrode includes a polycrystalline silicon oxide or polycide layer deposited on the gate oxide layer and a low resistance layer deposited on the polycide layer. The lower resistance layer contains silicide such as WSiO.sub.2, MoSi.sub.2, TaSi.sub.2 or TiSi.sub.2 or metal such as W, Mo, Ta or Ti. This double-layer structure is covered with a phosphor-doped silicon oxide layer, and the electrode layer is electrically connected to source and drain regions via contact holes which are formed in the phosphor-doped silicon oxide layer. A prerequisite with a gate electrode layer is that it has sufficiently low resistance. Such low resistance is usually attained by subjecting a dopd polycrystalline silicon layer and a low resistance layer which in combination constitute a gate electrode layer to heat treatment. Especially, as the integration density becomes higher, the gate electrode layer having a strip-like configuration becomes narrower and therefore the heat treatment for lowering the resistance is indispensable. A problem with such heat treatment is that it is apt to cause the two sublayers of the gate electrode layer to react on each other.
Generally, a prerequisite with a semiconductor IC device having high integration density is that the undulation on the surface of the device be reduced to prevent a wiring layer provided on that surface from being broken due to the undulation. To meet this requirement, the double-layer gate electrode structure should preferably be configured such that the polycrystalline silicon layer which constitutes the gate electrode layer has a minimum of thickness. A dilemmatic situation, however, is that reducing the thickness of the doped polycrystalline silicon layer is apt to cause mechanical stresses to act on a gate insulating layer during the course of heat treatment which is effected to lower the resistance as previously stated, resulting in a decrease in gate breakdown voltage.
A higher gate breakdown voltage is achievable with a gate electrode structure in which a gate electrode layer includes a polycrystalline silicon layer deposited on a silicon oxide layer, a barrier layer of WSi.sub.x or SiN deposited on the silicon layer, and a TiSi.sub.x layer provided on the barrier layer, as taught by T. Hori et al. in "Improvement of Dielectric Strength of TiSi.sub.x -Polycide-Gate System by Using Rapidly Nitrided Oxides," VLSI Symposium 87, pp. 63-64. In this kind of structure, electrical connection or contact is set up on the uppermost TiSi.sub.x layer by a wiring of aluminum. However, such a gate electrode structure has a drawback that the WSi.sub.x layer and the barrier layer of SiN or similar compound are extremely thin and therefore the thickness control during fabrication is difficult. Moreover, since the electrical contact is set up at a position just above the gate electrode, weak spots developed in the barrier layer immediately lead to the degradation of MOS characteristics.